The present invention relates to a memory cell configuration.
Memory components, such as DRAMs (Dynamic Random Access Memories) comprise a cell array and a peripheral driver area. Individual memory cells are arranged in the cell array.
A DRAM chip contains a matrix of memory cells which are arranged in the form of rows and columns and are driven via word lines and bit lines. Data are read from the memory cells or data are written to the memory cells by virtue of suitable word lines and bit lines being activated.
Normally, a DRAM memory cell contains a transistor connected to a capacitor. The transistor comprises, among other things, two diffusion regions which are isolated from one another by a channel which is controlled by a gate. Depending on the direction of the flow of current, one diffusion region is called the drain region and the other diffusion region is called the source region.
One of the diffusion regions is connected to a bit line, the other diffusion region is connected to the capacitor, and the gate is connected to a word line. By applying suitable voltages to the gate, the transistor is controlled such that a flow of current between the diffusion regions through the channel is turned on and off.
The progressive miniaturization of memory components is increasing integration density in stages. The increase in integration density means that the surface area available per memory cell is constantly falling.
To utilize the available surface area effectively, the selection transistor may be in the form of a vertical transistor in a trench above a trench capacitor. Memory cells having a trench capacitor and a vertical transistor are described in U.S. Pat. No. 5,208,657, for example. Conventionally, the trench capacitors are arranged in a rectangular pattern in that case. A problem with this is that the alignment accuracy of successive photolithographic exposure planes can have a disadvantageous effect on the operability of the memory cells.
The object of the present invention is to provide a memory cell configuration which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which provides for improved alignment tolerance for successive photolithographic exposure planes.
With the above and other objects in view there is provided, in accordance with the invention, a memory cell configuration, comprising:
a substrate having a substrate surface;
a first memory cell with a first trench capacitor and a first transistor disposed in the substrate, the first transistor having a first gate connect;
a second memory cell with a second trench capacitor and a second transistor disposed in the substrate, the second transistor having a second gate connect;
a first word line connected to the first gate connect of the first transistor;
a second word line running adjacent to the first word line and connected to the second gate connect of the second transistor;
a bit line crossing the first word line and the second word line and dividing the substrate surface into a first area and a second area;
wherein the first memory cell and the second memory cell are connected to the bit line, and a larger part of the first trench capacitor is disposed in the first area and a larger part of the second trench capacitor is disposed in the second area.
A primary advantage of the novel configuration is the alternate arrangement of the trench capacitors with respect to the bit line. Normally, directly adjacent trench capacitors connected to a bit line have been arranged in a row below or on one side of the bit line. This meant that the minimum distance between two adjacent trench capacitors was relatively short. With the inventive arrangement, the distance between adjacent trench capacitors is significantly increased, so that the trench capacitors in the inventive arrangement can firstly be designed to have a larger diameter, which means that their capacitance is increased, and secondly have a much improved alignment tolerance with respect to the word lines and the bit lines.
In accordance with an added feature of the invention, the bit line encloses an angle with the first word line of between 45xc2x0 and 90xc2x0, i.e., the bit line crosses the first word line at an angle of 45-90xc2x0. This arrangement permits a compact layout for the cell array with optimum utilization of space on the substrate surface.
In accordance with an additional feature of the invention, the bit line changes a direction of its course upon crossing a respective word line. This permits the distance between bit line and trench capacitor to be set such that the bit line contact can be designed to have a high degree of alignment tolerance.
In accordance with another feature of the invention, the first trench capacitor has six nearest adjacent trench capacitors, spaced respective distances from the first trench capacitor differing by at most 15%. In other words, the first trench capacitor has six adjacent trench capacitors whose distances from the first trench capacitor differ by at most 15%. This arrangement sets the distance between the adjacent trench capacitors such that the substrate surface has the greatest possible density of trench capacitors which are each at the greatest possible distance from their nearest adjacent trench capacitors and therefore influence one another as little as possible.
In accordance with a further feature of the invention, the first trench capacitor and further trench capacitors are arranged in corners of a hexagon. It is advantageous if, in addition to the first trench capacitor, further trench capacitors are arranged in the corners of a hexagon. The hexagonal arrangement is the densest packing in the plane, so that this arrangement permits efficient utilization of the substrate surface.
In accordance with a concomitant feature of the invention, the first trench capacitor is disposed in a bottom area of a trench formed in the substrate, and the first transistor is a vertical transistor formed above the trench capacitor in the trench. This permits very great use to be made of the available substrate surface by the trench capacitors, and the selection transistors are arranged in a space-saving manner in the upper area of the trench.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.